In order to increase the functional capacity of digital integrated circuits (ICs), IC designers necessarily implement progressively smaller geometries for metal-oxide-semiconductor field effect transistors (MOSFETs, or FETs) and other IC devices so that more circuitry per unit area may reside on an IC die. However, generally accompanying the smaller geometries and higher circuit densities are lower transistor breakdown voltages and higher power consumption, thus requiring the use of lower power supply voltages. Unfortunately, the use of a lower power supply voltage typically reduces the available amount of voltage margin, which allows an IC to operate properly in the presence of unavoidable variations in manufacturing processes, supply voltage, and operating temperature. As a result, circuit designs utilized in larger geometry ICs may become less fault tolerant when the same design is translated into an IC utilizing a smaller geometry.
An example of such a design is an IC read-only memory (ROM) circuit. A ROM is commonly employed to great advantage as a functional portion of a larger IC design, such as a control information store, or as a standalone IC. A typical IC ROM circuit arrangement from the prior art is shown in FIG. 1. In this case, an n-word by m-bit ROM comprises individual ROM bits 110 for each data bit to be stored. Each word of the ROM is enabled for reading by one of n separate READOUT signal lines, which are normally generated by an address decoder (not shown). At most one READOUT signal line is active at any particular time. The outputs of each ROM bit 110 associated with the same data bit of each word are connected to form an OUT signal line. Each OUT signal line is then an input for a signal buffer 120 associated with that bit of the data word to be read. Thus, the outputs of all signal buffers 120 collectively represent DATA, the m-bit data word currently being read.
FIG. 2 shows ROM bit 110 and signal buffer 120 in greater detail. ROM bit 110 is implemented by a single n-channel FET (NFET) NR, the gate of which is driven by one of the READOUT signals, READOUTx. The source of NFET NR is connected to either a ground reference via a ground connection 230, or to a power supply voltage reference VDD via power supply connection 240, depending on which of the two logic states, LOW or HIGH, is to be represented by ROM bit 110. When READOUTx is HIGH, NR turns ON, allowing the voltage at the source of NR to pass to OUT signal line OUTy, less the turn-on voltage across NR. The voltage on OUTy is then passed to the input of signal buffer 120, which in this case is a standard complementary MOS (CMOS) pair consisting of a p-channel FET (PFET) PB and an NFET NB. The output of signal buffer 120 drives the data signal line DATAy, which indicates the logic state of ROM bit 110 when READOUTx is HIGH. The use of single NFET NR in FIG. 2 ensures that the space required by ROM bit 110 is minimal, thereby allowing several thousand ROM bits 110 to occupy a relatively small space on the IC die. Additionally, ROM bit 110 dissipates virtually no power when READOUTx is in the LOW state, thus maintaining low overall power consumption for the ROM.
Unfortunately, as smaller device geometries are used for the ROM to increase IC functional capacity, the power supply voltage VDD is normally lowered, typically causing voltage margin problems, as depicted in FIG. 3. When READOUTx becomes active, the voltage level rises from VOFF substantially to VDD. Assuming power supply connection 240 (of FIG. 2) is utilized in ROM bit 110, the voltage level on OUTy becomes VDD less a significant voltage drop across NR, or VON, because the voltage on READOUTx at the gate of NR is essentially the same as that at the source, causing NR to drive a weak logic HIGH level. As seen in FIG. 3, VON may not be much higher than VTH, the threshold voltage at which signal buffer 120 perceives the voltage on OUTy as a logic HIGH instead of a logic LOW. The difference between VON and VTH is VM, the resulting voltage margin, which becomes smaller as the power supply voltage VDD is lowered with successive IC design generations implementing smaller device geometries. Thus, variations in the IC manufacturing process, along with variations in the operating temperature and power supply voltage of the IC, may cause VON to drop below VTH, thereby causing improper operation of the ROM.
From the foregoing, a new IC ROM design that minimizes the die area required for each ROM bit and dissipates almost no power when not being read, while allowing for greater voltage margins in the presence of relatively low power supply voltages, is desirable.
Embodiments of the invention, to be discussed in detail below, provide a ROM architecture that comprises a means for selectively driving one of two complementary logic state signal lines substantially to a voltage reference upon one of a plurality of readout signals becoming active so that a particular ROM bit may be read. The logic state of the ROM bit being read is indicated by which of the complementary logic state signal lines is being driven. A pair of inverting means is then cross-coupled with the two logic state signal lines so that the logic level of each logic state signal line is inverted and driven onto the opposing logic state signal line, resulting in both lines being driven to their proper state, even though only one logic state signal line is being driven directly as a result of the active readout signal. Therefore, only one of the logic state signal lines needs to be monitored to determine the proper state of the particular ROM bit being read.
Other embodiments of the invention take the form of a method of storing digital read-only data as a plurality of addressable bits. First, one of a pair of complementary logic state signal lines is selectively driven substantially to a voltage reference when one of a plurality of readout signals is active. The particular complementary logic state signal line that is being driven indicates the logic state of the ROM bit being addressed by the active readout signal. Each of the complementary logic state signal lines is then inverted and driven onto the opposing logic state signal line so that both lines are driven to their proper state, no matter which is being driven directly as a result of the active readout signal, allowing for other circuitry to read the logic state of the ROM bit from either line.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.